The Essence of Hardware Virtual Platforms
By Aditi Tamilarasu and Chethan Muralidhara
The automotive industry is consistently making strides towards the adoption of megatrends — connectivity, autonomous driving, and electrification. If we look at the market projection, as per the Markets and Markets report, the global connected car market size is expected to swell to USD 166.0 billion by 2025, from USD 53.9 billion in 2020. Taking these numbers into consideration, we can infer that the automotive industry is set to enter a phase of intense demands and challenges alike.
With passing time and the predicted exponential demands in terms of quantity and features, these technological marvels will require the production and design cycles to grow shorter, and upgrades to the hardware and software to become more frequent. Now, there are new players in the market like Tesla, who are coming up with aggressive update cycles and there are new technologies originating from a short cycle consumer market, which are making even relatively newer cars look obsolete in a short span.
The conventional manner of semiconductor development is, Design, Manufacture, and Validate, before developing the software for the hardware. This process is serial, tedious, and slow, and could hence be incapable of supporting such requirements.
According to Chethan, “To meet such challenges, engineers need to innovate and shorten the hardware-software production cycle of complex systems, while making no compromises on the extensive testing at relevant stages. It becomes a process of how to change the development procedures to use alternate resources and achieve deliverables in a parallel fashion as opposed to the usual serial order.”
Also, they would look for ways to maintain and reuse the legacy deliverables, how not to just test, but also debug faster, and so on. There is now a manner of development that addresses most of these kinks.
What is a Virtual Platform?
A Virtual Platform (VP) is a highly efficient software replica of a hardware system, that is simulated on a host and can execute software just as the hardware would. This technology can be used to model any hardware system, regardless of complexity. A VP can be built using SystemC and TLM standards.
SystemC, a special library of C++, enables a piece of code to behave like actual hardware by creating an illusion of multiple parallel processes happening at once, like simultaneous electrical events in a circuit. The means for communication between hardware components is defined by TLM (Transaction Level Modeling). TLM defines standard interfaces for SystemC models as it eases the integration of a system with several IPs and makes the simulation faster.
VP can model most components of embedded systems such as buses, clocks, pipelines, memory, registers, interconnects, instruction sets and interrupts using SystemC and TLM. SystemC has datatypes and inbuilt features that enable the easy implementation of such electrical complex entities, that not only behave in unique manners but also hold complex values that are encountered in an electrical scenario.
A VP can have different timing-related detailing. Depending on the time criticality of the application, one can model a VP to have its actions timed exactly like the hardware or approximately like it. Different types of VPs include Cycle Accurate (Very much accurate), Approximately timed (Close to the actual hardware behavior), Loosely timed (Possessing only critical time details), and Untimed models (Functionally accurate with no timing details).
Aditi explains, “A VP can also be abstracted according to the applications and can be functional, even if the hardware setup is partially modeled. The timing accuracy level and abstraction are major factors in deciding the applications of each model. The simulation speed will depend on the abstraction level; simulation speed will be fast for models which are abstracted at the function level and speed will be comparatively lesser for cycle-accurate models.”
Use cases of Virtual Platform
Hardware test case development:
IC/ASICs can be modeled at desired abstraction level (preferably timed model) using SystemC/TLM IEEE Library and then validated based on standard framework like UVM. These virtual ICs can be provided to the hardware team and used to develop hardware test cases before the actual hardware arrives. Once it arrives, these tests can be re-used to validate real hardware, thereby reducing the lead time of hardware validation.
ECU Modeling:
Standard interfaces (TLM) that are used to build virtual platforms provide a required framework for companies to exchange VP models across the IP supply chain. VP models of MCU from various SOC vendors can be taken and integrated with our custom IC/ASIC to form a complete virtual ECU, which represents the complete system functionally. The complete virtual ECUs can be used by the hardware or software team for various purposes like system-level design, development, and validation.
Architecture exploration:
Architecture exploration is the process of evaluating our specifications before the actual development starts. VP is very flexible to define a system architecture, which provides efficiency and performance for the desired application.
IPs / New architecture / Latest Designs / Architecture that are available from different vendors can be selected and explored to suit our needs. We can examine performance, resolve design challenges, perform HW/SW co-design, workload analysis, and examine correctness by means of simulation. Thus, the performance of new hardware for our needs can be gauged before the actual hardware arrives.
Hardware validation and Software development:
Before the actual hardware is manufactured, the software can be executed and validated on the virtual platform. VP runs binaries of the software that will finally run on actual hardware. So, additional efforts to make the software run the actual hardware is zero ideally. Initially, a basic test can be written to validate the virtual models, and the validated models can be provided to software teams for further software development. Any type of software i.e. Boot loaders, Drivers, Firmware, Bare-metal, AUTOSAR based, and any complex OS-based software can be developed using VP.
Depending on the type of the software and based on needs, different types of VP can be used i.e. cycle-accurate models, function-accurate models, timed models, untimed models et cetera. Another big advantage of VP is that it can be developed phase by phase and delivered to the software team, which will lead to HW/SW co-development as well. To conclude, we can say that the software can be developed well in advance which will further lead to a reduction in the time to market.
Cloud-based virtualization:
In recent times, continuous integration systems have become an integral part of the actual development and validation process. CI systems are very much necessary, especially for complex software development, which involves different teams in different geographical locations. Sometimes, it will be a tedious job to integrate actual target hardware into a CI environment, which might need some manual effort or continuous maintenance. This could lead to the entire process becoming more time-consuming.
To overcome the aforementioned difficulties, virtual platforms can be integrated into a CI environment, where we can install them on a server or in the cloud. These VPs in the cloud can be utilized for software development, running regression tests for every release and tagged version, and automating the report generation. SW developers can use this platform interactively wherever beneficial. Also, it can be extended to validate and simulate the functions with the ability of night validation runs.
Conclusion
Employing VP in the automotive-semiconductor production cycle is beneficial for many use cases spanning all over from product selection to production. There is an incredible degree of flexibility in the abstraction levels and the timing aspect that helps accommodate a wide range of applications. The use cases described above are based on the internal applications of our projects and the corresponding outcomes.
This approach has proven to decrease product development time by at least a few months and can potentially be utilized to define and develop many complex systems for Artificial Intelligence, IoT-based products, Automated Driving, Braking Systems, Infotainment, Transmission, Safety, and security, among others.
